The invention relates to a semiconductor device comprising a semiconductor body having a major surface and a first semiconductor region of a first conductivity type, which adjoins this major surface and which constitutes a first electrode zone common to several transistor structures, which transistor structures have a second semiconductor zone of a second conductivity type opposite to the first conductivity type, which extends from the major surface in the semiconductor body down to a smaller depth than the first semiconductor region. The the second semiconductor zone forms with the first semiconductor region a first pn junction, which terminates at the major surface while forming at this major surface a first outer edge of the second semiconductor zone. Plural second electrode zones are present which are associated with the transistor structures and which are constituted by third surface zones of the first conductivity type, which are located within the second semiconductor zone are separated by a second pn junction from the second semiconductor zone, wherein the second pn junction terminates at the major surface while forming at the major surface a second outer edge of each of the third surface zone. Between each of the third surface zones and the common first electrode zone a channel region is present which underlies an insulating layer, each of the channel regions being separated by the insulating layer from a first conductive layer serving as an insulated gate, while the third surface zones are provided at the major surface with an electrical connection formed by a second conductive layer.
Such a semiconductor device is know from Dutch Patent Application No. 7812488, which has been laid open to public inspection since July 2, 1979 and corresponds to U.S. Pat. No. 4,208,530. The known device described therein is an integrated logic circuit, in which the second semiconductor zone in each of the transistor structures is common to two or more third surface zones, while the electrical connections of these third surface zones are separated from each other and form logic signal outputs, the transistor structures each having a single logic signal input.
The aforementioned known integrated circuit is constructed according to the VMOS technology. Each of the transistor structures is a logic gate circuit which has the second semiconductor zone as signal input. The first semiconductor region is a common source electrode and the signal outputs are the drain electrodes constituted by the third surface zones adjoining V-shaped grooves. A bias current is supplied to each of the signal inputs by means of a MOS transistor, which has a channel region which adjoins the major surface and is located between a further surface zone of the second conductivity type acting as a source zone and the second semiconductor zone acting as a drain zone. The insulated gates of these MOS transistors serving for the current supply are connected to the common source zone of the VMOS switching transistors.
The gate circuits described have a comparatively large capacitance between their logic signal input and the common source zone. The surface area of the relevant pn junction is comparatively large and moreover the voltage applied across this pn junction is very small. Furthermore, the first pn junction between this signal input and the common source zone can readily become conducting in the forward direction during operation. This results in current losses, while moreover the operation of the gate circuits thus can be relatively strongly dependent on the operating temperature of the integrated circuit.
The V-shaped grooves of the switching transistors and hence also the insulating layer serving as a gate dielectric and the insulated gates are formed after the various dopings have already been provided in the semiconductor body. This means that the drain zones have to be chosen so large that after etching the V-shaped grooves, even if the mask required for this etching is not aligned fully correctly, all drain zones are still sufficiently large in order that the electrical connection formed by the second conductive layer can be provided on this zone. Furthermore, the gates of the MOS transistors serving for the current supply are provided simultaneously with those of the VMOS transistors and consequently also after the doping treatments. As a result, these current-supply transistors occupy a comparatively large area, while they have a comparatively large capacitance between their gate and their drain zone.